杜源

通信工程系 博导

个人简历

杜源,副教授,博导

2009年本科毕业于东南大学吴健雄学院(强化班)信息工程专业,2012年硕士,2016年博士均毕业于美国加州大学洛杉矶分校(UCLA),博士期间师从美国国家工程院院士、美国发明学院院士张懋中(M.C. Frank Chang) 教授,从事高速射频/光互联芯片、异构计算芯片设计研究,先后承担多项美国权威机构资助课题,获得博通(Broadcom)青年学者基金。博士毕业后,作为美国耐能公司(Kneron)创始团队核心成员,完成业内首款面向智能家居物联网的人工智能芯片量产。杜源博士在IEEE权威期刊及行业顶级会议上发表论文30余篇,包括3篇JSSC,2篇ISSCC,2篇VLSI,获得授权美国专利11项,并获IEEE Circuits and Systems Society(电路与系统学会)达林顿(Darlington)最佳期刊论文奖。主持国家自然科学基金青年项目,科技部重点研发计划青年科学家项目,江苏省自然科学基金青年项目,中国计算机学会(CCF)-蚂蚁科研基金项目等。先后入选国家级青年人才(2019)、华为“紫金学者” (2020)、江苏省“双创人才” (2021)等,目前是IEEE高级会员,IEEE CASS VSA技术委员会委员等。现阶段主要从事高速芯片互联与智能计算方向的科研工作。

诚邀有志于共同探索高速互联、智能计算、感知芯片设计的同学以及海内外科研人员加盟,更多研究方向信息请点击

研究方向

高速互联芯片设计:Chiplet芯粒间/存储器与加速器间/传感器与加速器间高速互联,高速光通信时钟数据恢复,有线/无线高速SerDes Transceiver等;

智能计算与感知芯片设计:端上处理的人工智能芯片,存内计算芯片,感算一体芯片

主要课程

 《高级模拟与射频集成电路设计与实践》

代表成果

1.高速互联:

[1.1] Y. Du, et.al, A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection, in IEEE Journal of Solid-State Circuits, vol. 52, no. 4, pp. 1111-1122, April 2017 [IEEE Xplore][PDF]

[1.2] Y. Kim et al., A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications, in IEEE Journal of Solid-State Circuits, vol. 54, no. 6, pp. 1600-1612, June 2019

[1.3] J. Du, et.al, A 28-mW 32-Gb/s/pin 16-QAM Single-Ended Transceiver for High-Speed Memory Interface, 2020 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, 2020, pp. 1-2

2.智能计算

[2.1] L. Du, et.al, A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 1, pp. 198-208, Jan. 2018(IEEE CAS Dalington Best Paper, 2021) [IEEE Xplore][PDF]

[2.2] Z. Shao et al., Memory-Efficient CNN Accelerator Based on Interlayer Feature Map Compression, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 2, pp. 668-681, Feb. 2022 [IEEE Xplore] [PDF]

[2.3] L. Du, et.al, A Reconfigurable 64-Dimension K-Means Clustering Accelerator with Adaptive Overflow Control, in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 4, pp. 760-764, Apr. 2020.

3.新型计算器件、新型计算架构

[3.1] Y. Du, et al., Characterization of Programmable Charge-Trap Transistors (CTTs) in Standard 28-nm CMOS for Nonvolatile Memory and Analog Arithmetic Applications, in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 7, no. 1, pp. 10-17, June 2021 [IEEE Xplore][PDF]

[3.2] Y. Du, et al., An Analog Neural Network Computing Engine using CMOS-Compatible Charge-Trap-Transistor (CTT), in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 10, pp. 1811-1819, Oct. 2019 [IEEE Xplore][PDF]

[3.3] Y. Xiao, W. Fan, Y. Du, L. Du and M. -C. F. Chang, CTT-based Non-Volatile Deep Neural Network Accelerator Design, 2021 18th International SoC Design Conference (ISOCC), 2021, pp. 258-259[IEEE Xplore][PDF]

4.传感及物联网系统

[4.1] H. Shui, et.al, A Low-Power High-Accuracy Urban Waterlogging Depth Sensor Based on Millimeter-Wave FMCW Radar. Sensors 2022, 22, 1236.

[4.2] Y. Mei, et.al, A Reconfigurable Permutation Based Address Encryption Architecture for Memory Security, 2020 33rd IEEE International System-on-Chip Conference (SOCC), Sep, 2020

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