Yuan Du (S’14-M’17-SM’21) received his B.S. degree with honor from Southeast University (SEU), Nanjing, China, in 2009, and his M.S. and his Ph.D. degree both from Electrical Engineering Department, University of California, Los Angeles (UCLA), in 2012 and 2016, respectively. Since 2019, he has been with Nanjing University, Nanjing, China, as an Associate Professor. Previously, he worked on edge AI accelerators in Kneron Corporation, San Diego, CA, USA from 2016 to 2019, as a leading hardware architect. He has authored or co-authored more than 60 technical papers in international journals and conferences and holds over 30 patents. His current research interests include designs of high-speed inter-chip/intra-chip interconnect circuits, RFICs, and machine-learning hardware accelerators. He was the recipient of the Microsoft Research Asia Young Fellow (2008), Southeast University Chancellor’s Award (2009), Broadcom Fellow (2015), and IEEE Circuits and Systems Society Darlington Best Paper Award (2021).

1. High-speed Interconnects and SerDes ICs

2. RF/mmWave ICs

3.Mixed-signal Computing Engineer ICs for AI

1. 《Application and Practice of Large Language Models in Chip Design》

2. 《Advanced Analog and RF ICs Design》

3. 《Introduction Course for Integrated Circuit Major》

1.High-Speed Interface Circuits and Systems：

[10] Ma, L. Yang, Y. Li and Y. Du, Noncontact Integration of Photonic IC and Electronic IC via Inductively Coupled Interconnects, in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 15, no. 1, pp. 232-234, Jan. 2025

[9] T. Ma, Y. Xu, X. Cheng, J. Guo and Y. Du, Channel Capacity Analysis of Mid-Range Multigigabit Transmission Over Dielectric Waveguides, in IEEE Transactions on Microwave Theory and Techniques, vol. 73, no. 5, pp. 2512-2522, May 2025 [IEEE Xplore link][2025-TMTT-High-speed-Channel-Analysis-Dielectric-Wave.pdf]

[8] X. Lu et al., A Non-Centralized Routing Scheme with Phase-Caching CDR for Nanosecond-Level Optical Switching Systems, 2023 IEEE 15th International Conference on ASIC (ASICON), Nanjing, China, 2023 

[7] Y. Wu, T. Li, Z. Shao, L. Du and Y. Du, An Efficient Design Framework for 2×2 CNN Accelerator Chiplet Cluster with SerDes Interconnects, 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), Hangzhou, China, 2023

[6] J. Lv, L. Du and Y. Du, A W-band Phase-Locked Loop with a Robust Injection-Locked Frequency Divider, 2023 8th International Conference on Integrated Circuits and Microsystems (ICICM), Nanjing, China, 2023 

[5] Q. Liu, L. Du and Y. Du, A 0.90-Tb/s/in 1.29-pJ/b Wireline Transceiver With Single-Ended Crosstalk Cancellation Coding Scheme for High-Density Interconnects, in IEEE Journal of Solid-State Circuits, vol. 58, no. 8, pp. 2326-2336, Aug. 2023 [IEEE Xplore link][2023-JSSC-0.9Tbps-per-inch-XTCC.pdf]

[4] XU Zhihang, XU Yongye, MA Tongchuan, DU Li, DU Yuan. 3D Contactless Chiplet Interconnects for CMOS Image Sensor[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3150-3156.

[3] Y. Hui et al., A CNN-based One-shot Blind RX-side-only Equalization Scheme for High-speed SerDes links, 2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS), Abu Dhabi, United Arab Emirates, 2024

[2] J. Du, J. Zhou, C. -J. Liang, B. Hu, Y. Du and M. -C. F. Chang, A 28-mW 32-Gb/s/pin 16-QAM Single-Ended Transceiver for High-Speed Memory Interface, 2020 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, 2020

[1] Y. Du et al., A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection, in IEEE Journal of Solid-State Circuits, vol. 52, no. 4, pp. 1111-1122, April 2017  [IEEE Xplore link][2017-JSSC-16Gbps-RFI.pdf]

2. Mixed-signal Computing Circuits and Systems：

[10] C. Xie, Z. Shao, M. Zhang, Y. Du and L. Du, RAC-NAF: A Reconfigurable Analog Circuitry for Nonlinear Activation Function Computation in Computing-in-Memory, in IEEE Journal of Solid-State Circuits, vol. 60, no. 10, pp. 3738-3748, Oct. 2025

[9] A. Jiang, L. Du and Y. Du, GroupQ: Group-Wise Quantization With Multi-Objective Optimization for CNN Accelerators, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 43, no. 7, pp. 2071-2083, July 2024

[8] L. Li et al., Optoelectronic Computing Evaluation and Deployment Platform Based on a 256-MAC Silicon Photonic Chip, 2024 IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, 2024

[7] Y. Li, L. Du and Y. Du, A Column-Parallel Time-Interleaved SAR/SS ADC for Computing in Memory with 2-8bit Reconfigurable Resolution, 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), Hangzhou, China, 2023

[6] Y. Lin et al., An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 11, pp. 4985-4995, Nov. 2024

[5] Y. Bai et al., An Efficient High-Throughput Structured-Light Depth Engine, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 8, pp. 1047-1058, Aug. 2022

[4] C. Xie, Z. Shao, N. Zhao, Y. Du and L. Du, An Efficient CNN Inference Accelerator Based on Intra- and Inter-Channel Feature Map Compression, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 9, pp. 3625-3638, Sept. 2023

[3] Y. Du, L. Du, W. Fan, Y. Xiao and M. -C. F. Chang, Characterization of Programmable Charge-Trap Transistors (CTTs) in Standard 28-nm CMOS for Nonvolatile Memory and Analog Arithmetic Applications, in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 7, no. 1, pp. 10-17, June 2021

[2] Y. Du et al., An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT), in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 10, pp. 1811-1819, Oct. 2019  [IEEE Xplore link][2019-TCAD-CTT-Analog-Neural-Network-Computing-Engine.pdf]

[1] L. Du et al., A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 1, pp. 198-208, Jan. 2018  [IEEE Xplore link][2018-TCASI-NPU-Best-Paper.pdf]

3. AI-EDA for Analog and High-speed Interface Circuits：

[5] A Large Language Model-based Multi-Agent Framework for Analog Circuits' Sizing Relationships Extraction [https://arxiv.org/abs/2506.18424]

[4] DiffCkt: A Diffusion Model-Based Hybrid Neural Network Framework for Automatic Transistor-Level Generation of Analog Circuits [https://arxiv.org/abs/2507.00444] 

[3] W. Chen et al., AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design, 2025 International Symposium of Electronics Design Automation (ISEDA), Hong Kong, China, 2025

[2] H. Xu et al., Image2Net: Datasets, Benchmark and Hybrid Framework to Convert Analog Circuit Diagrams into Netlists, 2025 International Symposium of Electronics Design Automation (ISEDA), Hong Kong, China, 2025

[1] W. Li, X. Chen, L. Du and Y. Du, A Strong-Arm Comparator Layout Design with Combined Expert Knowledge and Intelligent Optimization Algorithm in 65nm CMOS, 2023 8th International Conference on Integrated Circuits and Microsystems (ICICM), Nanjing, China, 2023