1. W. Li, J. Lin and Z. Wang, A 124-Gb/s Decoder for Generalized Integrated Interleaved Codes, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 8, pp. 3174-3187, Aug. 2019
2. J. Tian, S. Song, J. Lin and Z. Wang, Efficient T-EMS Based Decoding Algorithms for High-Order LDPC Codes, in IEEE Access, vol. 7, pp. 50980-50992, 2019
3. C. Zhu, R. Liang, J. Lin, Z. Wang and L. Li, Analysis and Design of a Large Dither Injection Circuit for Improving Linearity in Pipelined ADCs, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 9, pp. 2008-2020, Sept. 2019
4. H. Cui, J. Lin and Z. Wang, An Improved Gradient Descent Bit-Flipping Decoder for LDPC Codes, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 8, pp. 3188-3200, Aug. 2019
5. W. Li, J. Tian, J. Lin and Z. Wang, Modified GII-BCH Codes for Low-Complexity and Low-Latency Encoders, in IEEE Communications Letters, vol. 23, no. 5, pp. 785-788, May 2019
6. M. Wang, Z. Wang, J. Lu, J. Lin and Z. Wang, E-LSTM: An Efficient Hardware Architecture for Long Short-Term Memory, in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 9, no. 2, pp. 280-291, June 2019
7. Y. Zhou, J. Lin and Z. Wang, Improved Fast-SSC-Flip Decoding of Polar Codes, in IEEE Communications Letters, vol. 23, no. 6, pp. 950-953, June 2019
8. Y. Wang, J. Lin and Z. Wang, FPAP: A Folded Architecture for Energy-Quality Scalable Convolutional Neural Networks, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 1, pp. 288-301, Jan. 2019
9. Z. Wang, J. Lin and Z. Wang, Hardware-Oriented Compression of Long Short-Term Memory for Efficient Inference, in IEEE Signal Processing Letters, vol. 25, no. 7, pp. 984-988, July 2018
10. J. Wang, J. Lin and Z. Wang, “Efficient hardware architectures for deep convolutional neural network”, IEEE Trans. Circuits Syst. I, Reg. Papers, vol.65, no.6, pp. 1941-1953, Jun. 2018 (Transactions on Circuits and Systems Top 10 Downloaded May 2018)
